1. Field of the Invention
Embodiments of the invention relate to a level shifter for a liquid crystal display.
2. Discussion of the Related Art
An active matrix liquid crystal display includes a thin film transistor (TFT) as a switching element in each pixel. The active matrix liquid crystal display may be manufactured to be smaller than a cathode ray tube (CRT) and thus may be applied to display units of portable information appliances, office equipments, computers, etc. Further, the active matrix liquid crystal display may be applied to televisions and thus is rapidly replacing the cathode ray tube.
The liquid crystal display includes a liquid crystal display panel, a backlight unit providing the liquid crystal display panel with light, a data driving circuit for supplying a data voltage to data lines of the liquid crystal display panel, a gate driving circuit for supplying a gate pulse (or scan pulse) to gate lines (or scan lines) of the liquid crystal display panel, a timing controller for controlling operation timings of the data driving circuit and the gate driving circuit, etc. The liquid crystal display further includes a power supply device for generating the data voltage of the liquid crystal display panel, an on-voltage VGH and an off-voltage VGL of the TFT, and a power voltage VCC of the data and gate driving circuits and the timing controller.
The power supply device of the liquid crystal display is integrated into one integrated circuit (IC). An IC, in which the power supply device is embedded, is called a power IC below. When a power switch of the liquid crystal display is switched on, an input voltage Vin of the power IC rises.
The power IC of the liquid crystal display has a under voltage lock out (UVLO) function. When the input voltage Vin of the power IC reaches a previously determined level of the UVLO, the power IC generates an inner logic voltage VL and enables an inner logic. The power IC generates an output voltage Vout when the inner logic is enabled.
The gate driving circuit of the liquid crystal display includes a level shifter and a shift register. With the development of a gate-in panel (GIP) process technology, the shift register may be formed on a substrate, on which a TFT array of the liquid crystal display panel is formed, along with the TFT array. The level shifter may be formed on a printed circuit board (PCB) electrically connected to the substrate of the liquid crystal display panel. The level shifter outputs clock signals swinging between the gate high voltage VGH and the gate low voltage VGL under the control of the timing controller. The gate high voltage VGH is set to a voltage equal to or greater than a threshold voltage of the TFTs included in the TFT array of the liquid crystal display panel. The gate low voltage VGL is set to a voltage less than the threshold voltage of the TFTs included in the TFT array of the liquid crystal display panel. The shift register sequentially shifts the clock signals received from the level shifter and sequentially supplies the gate pulse to the gate lines of the liquid crystal display panel.
As shown in FIG. 1, the level shifter includes a logic circuit 50, a pull-up transistor PT, a pull-down transistor NT, etc. The pull-up transistor PT may be implemented as a p-type metal oxide semiconductor field-effect transistor (MOSFET), and the pull-down transistor NT may be implemented as an n-type MOSFET.
According to a power-on sequence, the gate low voltage VGL is supplied to the level shifter, and the gate high voltage VGH is supplied to the level shifter after a time of several milliseconds (msec) passed. In the process of the power-on sequence, when the gate high voltage VGH supplied to the level shifter reaches a predetermined level of the UVLO, the logic circuit 50 of the level shifter is enabled and starts to operate. When the logic circuit 50 is enabled and starts to normally operate after the power-on sequence, the logic circuit 50 generates an output for controlling on-operations and off-operations of the pull-up transistor PT and the pull-down transistor NT in response to the clock signals received from the timing controller. The pull-up transistor PT supplies the gate high voltage VGH to an output terminal in response to a first output of the logic circuit 50 and rises a clock signal CLK. The pull-down transistor NT discharges an output terminal to the gate low voltage VGL in response to a second output of the logic circuit 50 and falls the clock signal CLK.
When the power switch of the liquid crystal display is switched on, the power IC sequentially outputs the gate low voltage VGL and the gate high voltage VGH in conformity with the previously determined power-on sequence. When the gate high voltage VGH rises to a voltage equal to or greater than the predetermined level of the UVLO, the level shifter is enabled and may stably generate a normal output.
In the process of the power-on sequence, before the gate high voltage VGH is input to the level shifter, the output of the logic circuit 50 is floated. Hence, a gate voltage of the pull-up transistor PT and a gate voltage of the pull-down transistor NT may unstably swing in the process of the power-on sequence. In this instance, as shown in FIG. 2, before the gate high voltage VGH is supplied to the level shifter, the output CLK of the level shifter unstably swings. The unstable output of the level shifter may temporarily lead to erroneous operations of the shift register and the pixels of the liquid crystal display panel in an initial state where the liquid crystal display is just powered on.